By Hong Shen (auth.), Anu G. Bourgeois, S. Q. Zheng (eds.)

ISBN-10: 3540695001

ISBN-13: 9783540695004

ISBN-10: 354069501X

ISBN-13: 9783540695011

This ebook constitutes the refereed complaints of the eighth overseas convention on Algorithms and Architectures for Parallel Processing, ICA3PP 2008, held in Agia Napa, Cyprus, in June 2008.

The 31 revised complete papers offered including 1 keynote speak and 1 instructional have been rigorously reviewed and chosen from 88 submissions. The papers are geared up in topical sections on scheduling and cargo balancing, interconnection networks, parallel algorithms, dispensed platforms, parallelization instruments, grid computing, and software program systems.

**Read Online or Download Algorithms and Architectures for Parallel Processing: 8th International Conference, ICA3PP 2008, Cyprus, June 9-11, 2008 Proceedings PDF**

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**Extra info for Algorithms and Architectures for Parallel Processing: 8th International Conference, ICA3PP 2008, Cyprus, June 9-11, 2008 Proceedings**

**Example text**

The edges in the DAG correspond to the communication messages and precedence constraints among the nodes. The weight of an edge, which represents the amount of time needed to communicate the data, is called the communication cost of the edge. The source node of an edge incident on a node is called a parent of that node. Similarly, the destination node emerged from a node is called a child of that node. A node with no parent is called an entry node and a node with no child is called an exit node.

This algorithm computes a p-way partitioning that takes into account the resource capabilities of each Architecture Aware Partitioning Algorithms 47 processor and minimizes the total communication volume. The partitioning for the second phase is computed by utilizing a randomized greedy reﬁnement algorithm (similar to those used in MeTiS’s p-way partitioning algorithms) that moves vertices between partitions as long as such moves optimize the quality of the resulting decomposition. We used two diﬀerent approaches to assess the quality of the architectureaware partitioning.

The insight is that LPL does not suﬃciently penalize for cut edges across links that suﬀer from slower communication capabilities. For our model we assume that communication in either direction across a given link is the same, therefore e∗ (pi , pj ) = e∗ (pj , pi ), for i, j = 1, . . , p. We also assume that e∗ (pi , pi ) = 0, as the cost for any given processor to retrieve information from itself is incorporated in its computational cost w∗ (pi ). Although the existing heterogeneous partitioning algorithms assume a complete weighted architecture graph, we ﬁnd that this approach is not scalable and therefore avoid it.

### Algorithms and Architectures for Parallel Processing: 8th International Conference, ICA3PP 2008, Cyprus, June 9-11, 2008 Proceedings by Hong Shen (auth.), Anu G. Bourgeois, S. Q. Zheng (eds.)

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